AMD confirms production ramp of its EPYC 'Venice' server CPUs on TSMC's 2nm process

AMD's Zen 6-based 'Venice' CPUs become the first HPC product to enter volume production on TSMC's 2nm process; 'Verano' to follow soon.

AMD confirms production ramp of its EPYC 'Venice' server CPUs on TSMC's 2nm process
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TL;DR: AMD has begun full-scale production of its 6th Gen EPYC "Venice" processors using TSMC's 2nm process, featuring up to 256 cores, a 70% performance boost, and doubled memory bandwidth. Venice targets HPC, cloud, and AI workloads, with future 2nm EPYC "Verano" optimized for efficiency and LPDDR support.
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AMD has announced the production ramp of its next-generation 6th Gen EPYC server processors, codenamed "Venice." This is a big milestone, as Venice is the first high-performance computing (HPC) product in the entire industry to enter volume production on TSMC's advanced 2nm process node. Production is currently underway at TSMC's facilities in Taiwan, with plans to later extend the ramp to TSMC's Arizona fabrication plant as well.

So what does "production ramp" mean, exactly? It refers to the transition from early, limited silicon runs into the full-scale, high-volume manufacturing needed to supply commercial customers. In other words, Venice has transitioned from an engineering sample to a production-ready state and is getting ready to ship at scale.

As for what Venice actually brings to the table, the numbers are quite impressive. The processor is built on AMD's new Zen 6 architecture and scales up to 256 cores, a 33% increase over the current EPYC "Turin" lineup's maximum of 192 cores. AMD projects a 70% performance improvement over Turin as well.

AMD confirms production ramp of its EPYC 'Venice' server CPUs on TSMC's 2nm process 5067

Moreover, per-socket memory bandwidth more than doubles to 1.6 TB/s, up from 614 GB/s, and CPU-to-GPU bandwidth also gets a 2x boost. These are significant gains for cloud and AI infrastructure deployments, where memory throughput and core density are critical considerations.

AMD is also planning to extend the 2nm lineup with "Verano," another 6th Gen EPYC processor that follows Venice on the same TSMC process. Verano is being optimized for performance per dollar per watt and will include native LPDDR support to meet the memory demands of agentic AI workloads. Meanwhile, AMD just recently launched the EPYC 8005 "Sorano" family as well, a Zen 5-based single-socket lineup with up to 84 cores targeting edge, telco, and cloud storage use cases.

All of this momentum is arriving at a time when AMD EPYC is absolutely dominating the data center space. According to an earlier report we covered, AMD EPYC CPUs captured a record 46.2% of server CPU revenue in Q1 2026, an all-time high. Venice is likely to push that number even further when it eventually arrives.

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News Source:amd.com

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Hassam is a veteran tech journalist and editor with over eight years of experience embedded in the consumer electronics industry. His obsession with hardware began with childhood experiments involving semiconductors, a curiosity that evolved into a career dedicated to deconstructing the complex silicon that powers our world. From benchmarking PC internals to stress-testing flagship CPUs and GPUs, Hassam specializes in translating high-level engineering into deep, unbiased insights for the enthusiast community.

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