TSMC says energy efficiency has overtaken raw performance as the top priority for AI chip customers

The AI boom has driven extraordinary demand for computing power, but it is now creating a constraint that raw performance alone cannot solve. Speaking at a conference in Amsterdam, TSMC Senior Vice President of Business Development Kevin Zhang said energy efficiency has overtaken computing performance as the defining priority for customers across the chip industry.

"The area customers most want improvement in is energy efficiency. This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center," Zhang told Reuters. The shift marks a major change for the chip industry as the era of simply packing more transistors onto a chip and calling it progress appears to be drawing to a close.

TSMC expects its A14 chips, due around 2028, to deliver more than 20% higher computing performance while cutting power consumption by up to 30% compared to its current N2 technology. Zhang added that while transistor density remains central to TSMC's plans, technologies such as advanced packaging, chip stacking, and photonics are becoming increasingly important in driving efficiency gains beyond what transistor scaling alone can achieve.

2

TSMC's upcoming A13 and A12 process technologies, both targeted for 2029, are not expected to require High-NA EUV lithography tools. TSMC is also targeting a 30% efficiency improvement per generation and says it is on track to deliver that even as chips approach 1MW power levels before the end of the decade.

Zhang also weighed in on Huawei's recently announced Tau Scaling Law, which aims to improve performance by accelerating data movement within chips. He said the underlying concept has "existed in the industry for years" and largely depends on tighter component integration enabled by technologies such as 3D stacking.

Analysts also say that while stacking more chip layers can increase transistor density, it can also raise power density and overheating risks, with manufacturing yields and costs posing additional barriers. With TSMC forecasting that 55% of all chips produced by 2030 will support AI and HPC applications, the pressure to deliver greater performance per watt will only intensify.