NVIDIA's next-gen 'Feynman' GPUs to be built with TSMC's 1.6 nm A16 process

With NVIDIA's Rubin and Rubin Ultra GPU architectures rolling out now and on the immediate horizon in the AI and Data Center spaces, the company's next-generation 'Feynman' architecture is in development. According to a new report from DigiTimes, NVIDIA's 'Feynman' GPU technology is targeting the second half of 2028 for mass production and release, and it's going to use TSMC's most cutting-edge process to date - A16.

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Yes, apparently NVIDIA will skip TSMC's N2 or 2nm process family for its 'Feynman' products and instead move to the more advanced A16 1.6nm process. This represents a significant jump, as Rubin and Rubin Ultra are based on TSMC's N3 process. However, separate to the node shrink, what makes this notable is that 'Feynman' will be the first NVIDIA technology to feature 3D chiplets via TSMC's System on Integrated Chips (SoIC) technology, backside power delivery, and next-generation packaging.

Compared to the 3nm Rubin and Rubin Ultra, this represents a major evolution in design. Of course, much of the timing depends on TSMC expanding capacity, with the DigiTimes report adding that the company is accelerating construction of its AP7 and AP8 facilities to ramp up SoIC production. This includes earlier-than-expected deployment for new equipment, cleanrooms, and various operations.

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Question #1

Which TSMC process node is NVIDIA reportedly using for Feynman, and how does it compare to Rubin/Rubin Ultra?

The report says NVIDIA is targeting TSMC's A16 1.6 nm process for Feynman. This is a jump from Rubin and Rubin Ultra, which are based on TSMC's N3 (3 nm) process.

Answered

Question #2

Why is skipping TSMC's N2/2nm process notable for NVIDIA's Feynman GPUs?

Skipping TSMC's N2/2nm process is notable because NVIDIA is jumping straight to TSMC's more advanced A16 1.6nm node for Feynman, representing a major node shrink from the 3nm Rubin architectures. The move is also significant because Feynman will be NVIDIA's first technology to use 3D chiplets via TSMC's SoIC technology, backside power delivery, and next-generation packaging, along with custom next-generation HBM and co-packaged optics to boost performance and bandwidth.

Answered

Question #3

What packaging and integration technologies will Feynman reportedly use (e.g., 3D chiplets, SoIC, backside power delivery)?

According to the primary article, Feynman is reported to use 3D chiplets via TSMC’s System on Integrated Chips (SoIC) technology, backside power delivery, and next-generation packaging. The report also says it will employ next-generation HBM and co-packaged optics (CPO) for very high bandwidth.

Answered

Question #4

What memory technology will Feynman GPUs reportedly use, and how is it described in the report?

They will use next-generation HBM memory, described in the report as next-generation HBM technology that leverages a custom design to boost performance.

Answered

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Although TSMC and NVIDIA haven't confirmed or responded to the report's claims, it suggests TSMC is aiming to hit 50,000 wafers by the end of 2027 to pave the way for Feynman's arrival in the second half of 2028. These new GPUs will also use next-generation HBM technology, leveraging a custom design to boost performance. Finally, as performance and bandwidth go hand in hand, Feynman will also leverage co-packaged optics (CPO), aka the speed of light, that could push bandwidth into the petabyte-per-second range.